Why RISC-V support is a big deal for Qualcomm and Android

As smartphone users, we carry an incredible amount of computing power in our pockets every day. Even today’s most affordable phones boast exponentially more processing power than, for example, the computer that helped guide Apollo 11 to the moon. And most of us can comfortably live out our smartphone-enhanced lives blissfully unaware of the advanced engineering that goes into the circuitry directly responsible for pushing the 1s and 0s that drive everything from the simplest modern electronics to AI supercomputers.

Partly with Qualcomm and Google’s inspiration, though, something’s happening to mobile chipset design right now that could advance smartphone engineering in a way we haven’t seen since smartphones first appeared. An increasingly relevant instruction set architecture called RISC-V stands to liberate engineers from the relatively restrictive technology that most smartphone systems-on-a-chip have relied on since their inception. Most consumers won’t directly notice the tangible outcomes of RISC-V implementation, but it could affect the mobile electronics industry in a big way, especially when it comes to Android-based devices.

RISC vs CISC chips

The technology behind nearly every modern smartphone falls into a relatively specific category of computer design. The Reduced Instruction Set Computer chipsets used in phones comprise nanometer-size transistors, and materials including copper and silicon, just like the Complex Instruction Set Computer microchips that Windows and many other desktop and laptop PCs use. But RISC self-contained chips use more streamlined instructions than CISC systems that have various math processors, voltage regulators, and memory controllers scattered across a mainboard.

The first microchips could be considered CISC chips, although nobody called them that until after 1980, when engineers behind increasingly refined RISC architectures sought to differentiate their approach to what the industry had already established. Broadly speaking, RISC chips use more streamlined instruction sets, but the concepts are somewhat abstract at this point, as CISC systems continue to incorporate design strategies that share a lot with RISC configurations.

To be clear, the terms exist partly as conceptual descriptions and marketing designations, and the divide between the two systems isn’t exactly definitive. Because while there are some broad distinctions between CISC and RISC operation, even industry-leading CISC designers Intel and AMD have long used RISC-like pipelines to decode complex instructions into micro-operations within their greater x86 designs.

Ultimately, spreading operations over multiple chip components (including RISC-like microcode) makes CISC designs potentially more versatile and demanding of hardware than strictly RISC systems, although the outcome does still depend on chipset implementation. In the case of x86 vs ARM instructions found in today’s PCs and smartphones, more powerful hardware calls for more electricity, which inevitably leads to more waste in the form of heat, neither of which works well with mobile electronics. While there have been some x86 smartphones, they never took off.

What are instruction sets, and how are some reduced?

A system’s ISA describes what functions a microchip can perform and what instructions a piece of software uses to communicate with the underlying hardware. Many chip designs, including what you could call CISC chips, encompass varying numbers of instructions and instruction complexity. Larger collections of longer and more variable instructions give software developers more freedom to take advantage of the implementation, but come with their own drawbacks in terms of efficiency and power requirements.

RISC instruction sets began as a way to standardize and simplify those instructions in order to streamline chip and software interaction, and increase efficiency and specialization. Limited selections of shorter, consistent-length instructions require less processing power since the commands are easier to store and parse. Load-store, or register-register architectures speed up calculations by keeping data in CPU registers (tiny storage spaces within the CPU where small bits of information are kept during cycles) rather than purging them once commands are executed. And the tendency of RISC systems to cycle fewer times per second than CISC systems reduces power draw and, therefore, waste heat.

While there are plenty of distinct ISAs both complex and reduced, only one matters when it comes to smartphones. Arm’s extensive IP ownership and vast experience in developing ARM ISAs affords its product considerable benefits over opposing technologies, not just in smartphones, but also other fast-growing industries including the automotive and data center industries.

ARM, the ubiquitous RISC ISA

The companies that design specific chipset architectures own those architectures as IP, and license them out for other manufacturers to use. In the desktop and laptop PC landscape, Intel and AMD own most of the consumer-facing CISC architecture IPs. A legally negotiated cross-licensing agreement allows the two companies to easily share technologies, which enables the ever-evolving processor wars that enthusiasts have bickered about online for ages.

Modern RISC chips and the related ISAs are a different story. Founded in 1990, Arm Holdings got a leg up from burgeoning Apple Computers in the form of $3 million investment, in addition to tools and engineers from chip maker VLSI and vendor Acorn Computers. More than three decades after this head start, Arm’s practical patent stranglehold has essentially turned it into the gatekeeper of the SoC world. Its most notable customers include companies such as Apple, Qualcomm, and Samsung, competitors figuratively at each others’ throats with every hardware and software innovation.

Why doesn’t Intel compete with ARM in the RISC ISA space?

As one of the world’s behemoths in CISC microchip production, you’d think Intel has the resources to develop its own competitor to the instruction set developer that’s started to look more and more like a monopoly. Intel does actually produce RISC components, and integrates them within its larger microprocessors. But those reduced instruction micro-sets only serve as part of a whole, and aren’t designed to operate as entire SoCs.

Intel did launch a RISC-V project called Pathfinder in August 2022, in an attempt to encourage community inroads in the growing ISA. A mere five months later, Intel axed the new project with little fanfare. As the electronics market has faltered recently for a variety of reasons (the Covid-19 pandemic not the least of which), Intel had put the kibosh on several other ventures just prior to the demise of Pathfinder. Pat Gelsinger, Intel CEO, went on to explain that Intel “will continue to navigate the short-term challenges while striving to meet our long-term commitments,” which apparently do not include RISC-V development.

Source: Anandtech

The 2018 Senwa LS9718 was likely one of the last phones with an x86 processor inside

Since Intel largely profits off chipmaking, rather than entire, vertically integrated systems (like Apple) or licensing an ISA (like Arm) to many specialized chipmakers, it doesn’t have the same pathways to profitability with potential mobile chipsets as with its already established technology. The rise of companies like Nvidia and Taiwan Semiconductor and their various custom microchip ventures only compounded Intel’s struggles, as its network switch business NEX ended up one of the casualties of 2022’s drastically reduced year-on revenue. As big as it is, Intel couldn’t power through the inertia of entering a new field.

The corporate struggles of Arm and its ownership group

Today’s massive selection of great mobile electronics shows that Arm ISAs clearly work fine for their intended use. But while nothing’s inherently wrong with Arm’s ubiquitous instruction set, its 99% smartphone SoC market share puts it somewhat at the mercy of the market. As mobile technology plateaus and new mobile device releases get more iterative than innovative, smartphone sales have slumped in recent years, and there’s no headroom left for growth in some of its major markets that are hampered by decreased consumer discretionary spending.

In the background, Japanese investment giant Softbank Group also saw multiple less-than-ideal returns in the last two years. Even dumping its remaining Uber holdings at a profit couldn’t stop it from posting a record $32 billion loss over the fiscal year ending in 2023.

Amidst this downturn, Softbank also tried offloading Arm to microchip manufacturing giant Nvidia, a company that major names in the tech industry have strongly criticized for its practices. Hermann Hauser, Arm co-founder, went so far as to predict the sale would result in the creation of “another US technology monopoly.” Over 18 months of deliberation, U.S. administrative and regulators, as well as those from major markets in the UK and EU, applied significant pressure to the deal, which Softbank and Nvidia ultimately terminated.

Instead of a clean, $66 billion sale that would have provided Softbank with a sizable cash infusion, it spun off the property in a stock IPO valued at $54 billion. That translated to a nearly $5 billion profit for Softbank, but still a far cry from its previous $64 billion valuation. And as is the case with nearly all public enterprises, Arm’s new investors insisted that the line must go up, which led Arm to drastically increase licensing costs, putting significant pressure on Arm’s formerly somewhat satisfied partners.

While profit is still profit, reports indicate a less-than-rosy outlook for some parts of Arm’s operation. Well before the IPO, The Financial Times got wind that Arm planned to overhaul its business model and raise licensing fees, which would affect every single smartphone manufacturer, and leaders across every industry that relies on ARM ISAs. While it apparently hadn’t yet done that as of the post-IPO earnings report, it did post a poor forecast, partly blaming the uncertainty of its upcoming licensing deals. Further in-depth reports also hint that Arm’s ready to alter less-profitable licensing contracts like its agreement with Apple, which heavily favors the iconic electronics and lifestyle manufacturer.

Arm’s continued legal quandaries

To add further financial insult to injury, in 2022 Arm sued Qualcomm over its $1.4 billion acquisition of chipmaker Nuvia, claiming that the sale violated Nuvia’s licensing terms. Arm claims Qualcomm’s purchase gives it no right to absorb the work that Nuvia had done under its licensing agreement, and Qualcomm basically told Arm to go away and mind its own business. That lawsuit is still in progress, but it really boils down to the world’s leading ISA developer taking the legal screws to one of its biggest partners.

What’s more, as US-China trade wars have escalated over the last few years, China (the world’s biggest smartphone market by a wide margin) has moved to adopt the RISC-V ISA to circumvent aggressive tariffs and even some outright bans on US companies working with Chinese manufacturers. Following all this turmoil, Qualcomm took the next step toward reducing reliance on Arm’s market control by moving forward with multilateral adoption of RISC-V.

Enter RISC-V, the open-source mobile architecture

Qualcomm began integrating the RISC-V architecture into its chipset designs in 2019, but it was by no means the technology’s birth. Lars Bergstrom, Google Director of Engineering confirmed the company’s commitment at the 2022 RISC-V Summit, making a good case for the ISA’s relevance for years to come. Additional companies have echoed these efforts to free the industry from the clutches of the near-monopoly of Arm, creating a forward-thinking coalition of companies to develop the license-free instruction set and help it realize its potential.

And then there’s the recent news that caught even more consumers’ eyes than the 2022 rumors of upcoming RISC-V smartphones. Qualcomm’s October 2023 announcement that it was collaborating with Google to design its first mass-market RISC-V chipset, in this case for powerful, efficient Wear OS smartwatches, brought renewed excitement to the industry. But that’s not even the most recent development, as in November 2023, Tokyo-based Renesas Electronics Corporation became the first company to announce a fully developed, 32-bit, general-purpose RISC-V CPU core.

While you might be inclined to compare RISC-V to the way Android or Chrome works, due to the underlying open-source nature of both, it’s a step more revolutionary than that. Chrome and its underlying rendering engine, Chromium, are still spearheaded by a corporation, and the same is true for the Android Open Source Project, which is mostly developed behind closed doors until Google’s latest changes make it to the public.

Source: RISC-V

The big difference is that in this equation, Qualcomm doesn’t own RISC-V; no one company does, as RISC-V itself originated at UC Berkely and now falls under the purview of RISC-V International, with the specific intent of fostering open ISA collaboration. But Qualcomm and Google’s new RISC-V Snapdragon Wear project drew industry-wide attention to collaboration on the ISA that might just prove to be the future of mobile devices.

Why RISC-V is a good thing

While mobile SoC technology has continued to improve even under the watchful eye of Arm’s closed-source development and licensing fees, competition between industry leaders always benefits consumers, by nature. But the industry-wide potential of RISC-V development presents clear upsides beyond just adding another player to the game.

As Qualcomm itself lays out, the flexibility of the ISA’s feature set lets hardware and software developers alike tailor their development to their own goals. Working with a closed-source instruction set forces companies into a blanket set of features with limited customization potential. According to the company, this means faster development cycles and more positive design tweaks.

Enabling more specialized advancement also lets manufacturers control their own projects more closely, reducing licensing fees and reliance on third-party tools. If engineering firms and manufacturers can more easily improve their bottom line, it stands to reason that some of the benefits will be passed on to consumers in the form of better performance, more streamlined products, and improved reliability.

And just like the benefit of countless other projects, a readily available, community-reviewed architecture and codebase helps developers stay on their toes. This transparency not only helps companies plan out future investments and other resource allocation, but also get the jump on potential upcoming security issues before they become reality.

RISC-V benefits, in real-world consumer terms

RISC-V may well spur the genesis of more advanced SoCs, specialized processor cores, focused and powerful on-device machine learning algorithms, time- and effort-efficient software development packages, interesting and novel applications, and — this is a really big one — lowered research and development and hardware costs. As consumers, though, we might end up benefitting from these without ever even knowing unless we dig deep into what architecture our personal choice of smartphone or tablet is built around.

The most tangible benefits of the introduction of an ISA come in the back end. If a manufacturer can get their hands on a one-off chip design that dovetails perfectly with its chosen feature set, it’ll be able to (in an ideal world) release new device generations more quickly, with more noticeable upgrades in each one.

Increasingly specialized hardware could also pave the way for more companies to offer novel, cutting-edge services that push the boundaries of current electronics functionality. Consider what Google’s done in terms of machine learning-based features in its Pixel 8 series, which is pretty impressive, yet still built around hardware like the promising Snapdragon 8 Gen 3. The ability to experiment further with bespoke chip and OS design shows the potential to bring even more interesting, useful tools to life.

Making hardware and software design more accessible to all

One of the biggest overarching positives of RISC-V implementation is lowering the barrier of entry into the hardware and software development market. With no licensing fees, niche companies see more potential to start up and actually deliver truly novel products. Even individual software engineers may find it easier to jump into backend design, enabling all today’s as-yet-undiscovered geniuses to contribute to the ever-advancing state of consumer technology. That’s partly because RISC-V’s open-source nature also makes it considerably more attractive to educational institutions.

Finally, hand-in-hand with a lowered barrier of entry, are the obvious implications of lowered upfront and ongoing costs. Sure, we’re still talking about capitalism here, so slashed licensing allocations and a greatly reduced ongoing development budget will undoubtedly contribute somewhat to executive bonuses across the industry. But that reduced overhead, combined with a lowered barrier of entry and more dynamic possibilities, will also certainly improve the state of consumer electronics.

In short, RISC-V has the potential to really speed up the advancement of the entire market. There’s reason to believe open-source ISA adoption could ultimately help provide end-users with many more great phones, maybe even for less money.